AS & A Level Computer Science (9618)
Hardware and virtual machines Banker
16 questions · about 5% of the marks we indexed · examined in 9 of 9 sessions.
Practice questions
Original questions written by HomiLabs in the style of the exam, with answers and mark schemes. They are not
Cambridge past paper questions and have not been reviewed by Cambridge. Try each one before opening the answer.
Q1Boolean algebra & Karnaugh maps · Core · Paper 3 style · 5 marksNotation: ¬A means NOT A, A.B means A AND B, A + B means A OR B.A logic circuit has inputs A, B, C. Its output X = 1 for ABC = 001, 011, 101, 110 and 111, and X = 0 otherwise.
- (a) Complete the Karnaugh map for X. Use rows A = 0, 1 and columns BC = 00, 01, 11, 10. [2]
- (b) Draw loops around groups of 1s (describe each group) and write the simplified sum-of-products expression for X. [3]
Show answer
- (a) A \ BC | 00 01 11 100 | 0 1 1 01 | 0 1 1 1
2 marks all cells correct; 1 mark one error. Note column order 00, 01, 11, 10 (Gray code).
- (b) Groups: the four 1s in columns BC = 01 and 11 (both rows) → C; the pair A = 1, BC = 11 and 10 → A.B.X = C + A.B
1 mark group of four; 1 mark pair; 1 mark correct expression.
Notation: ¬A means NOT A, A.B means A AND B, A + B means A OR B.
- (a) Simplify A.B + A.¬B, stating the Boolean law used at each step. [2]
- (b) Simplify A + A.B, showing your working. [2]
Show answer
- (a) A.B + A.¬B = A.(B + ¬B) (distributive law)= A.1 (complement / inverse law: B + ¬B = 1)= A (identity law)
1 mark factorising; 1 mark final answer A with laws.
- (b) A + A.B = A.1 + A.B = A.(1 + B) = A.1 = A (absorption law)
1 mark factorising / using 1 + B = 1; 1 mark answer A.
Notation: ¬A means NOT A, A.B means A AND B, A + B means A OR B.
- (a) Apply De Morgan's laws to write each expression without a NOT over a bracket.(i) ¬(A.B.C)(ii) ¬(¬A + B)(iii) ¬(A + B + ¬C) [3]
Show answer
- (a) (i) ¬A + ¬B + ¬C(ii) A.¬B(iii) ¬A.¬B.C
1 mark each. The operator must change (AND ↔ OR) as well as each term being inverted.
Notation: ¬A means NOT A, A.B means A AND B, A + B means A OR B.
- (a) Complete each Boolean identity.(i) A + 0 = ?(ii) A.0 = ?(iii) A + ¬A = ?(iv) A.¬A = ?(v) A + 1 = ?(vi) A.A = ? [3]
Show answer
- (a) (i) A (ii) 0 (iii) 1 (iv) 0 (v) 1 (vi) A
3 marks all six; 2 marks four or five; 1 mark two or three.
Notation: ¬A means NOT A, A.B means A AND B, A + B means A OR B.F = 1 for these input combinations (ABCD): 0000, 0010, 1000, 1010, 0101, 0111, 1101, 1111. F = 0 for all other combinations.
- (a) Complete the Karnaugh map for F. Use rows AB = 00, 01, 11, 10 and columns CD = 00, 01, 11, 10. [2]
- (b) Identify the groups and write the simplified sum-of-products expression for F. [3]
- (c) State the single two-input logic gate, with inputs B and D, that gives the same output as F. [1]
Show answer
- (a) AB \ CD | 00 01 11 1000 | 1 0 0 101 | 0 1 1 011 | 0 1 1 010 | 1 0 0 1
2 marks all correct; 1 mark one or two errors.
- (b) Group of four corners (B = 0, D = 0) → ¬B.¬D; group of four in the centre (B = 1, D = 1) → B.D.F = ¬B.¬D + B.D
1 mark corner group (wrap-round); 1 mark centre group; 1 mark expression.
- (c) XNOR (F = NOT (B XOR D))
B1.
Notation: ¬A means NOT A, A.B means A AND B, A + B means A OR B.
- (a) Use De Morgan's laws and Boolean algebra to simplify Z = ¬(A + B).(A + ¬B). Show each step. [3]
- (b) Write ¬A.¬B as a single logic gate with inputs A and B. [1]
Show answer
- (a) ¬(A + B) = ¬A.¬B (De Morgan)Z = ¬A.¬B.(A + ¬B) = ¬A.¬B.A + ¬A.¬B.¬B= 0 + ¬A.¬B (A.¬A = 0; ¬B.¬B = ¬B)Z = ¬A.¬B
1 mark De Morgan step; 1 mark expansion; 1 mark final ¬A.¬B.
- (b) NOR (A NOR B)
B1.
Notation: ¬A means NOT A, A.B means A AND B, A + B means A OR B.A truth table for output P with inputs A, B, C has P = 1 for ABC = 010, 011, 110 and 111, and P = 0 for the other four rows.
- (a) Write the sum-of-products expression for P directly from the truth table. [2]
- (b) Use Boolean algebra to simplify your expression. Show your working. [3]
Show answer
- (a) P = ¬A.B.¬C + ¬A.B.C + A.B.¬C + A.B.C
1 mark two terms correct; 2 marks all four, joined by +.
- (b) = ¬A.B.(¬C + C) + A.B.(¬C + C)= ¬A.B + A.B= B.(¬A + A)= B
1 mark factorising C terms; 1 mark ¬A.B + A.B; 1 mark final B.
Notation: ¬A means NOT A, A.B means A AND B, A + B means A OR B.A Karnaugh map for output Q is given row by row (rows AB, columns CD in the order 00, 01, 11, 10):AB \ CD | 00 01 11 1000 | 1 1 0 001 | 1 0 0 111 | 1 0 1 110 | 0 0 1 0
- (a) Identify the groups and write the simplest sum-of-products expression for Q. [4]
Show answer
- (a) Group of four: rows AB = 01 and 11, columns CD = 00 and 10 (wrap-round left/right) → B.¬D.Pair: row AB = 00, columns CD = 00 and 01 → ¬A.¬B.¬C.Pair: rows AB = 11 and 10, column CD = 11 → A.C.D.Q = B.¬D + ¬A.¬B.¬C + A.C.D
1 mark each correct group (the group of four must use the wrap-round); 1 mark final expression. The pair 0000/0100 (¬A.¬C.¬D) is redundant: do not award the final mark if it is included.
Notation: ¬A means NOT A, A.B means A AND B, A + B means A OR B.
- (a) Use a Karnaugh map to simplify F = ¬A.B.¬C.D + ¬A.B.C.D + A.B.¬C.D + A.B.C.D + A.¬B.¬C.D + A.¬B.C.D. State the groups used. [4]
- (b) Factorise your answer and describe a circuit for it using two gates. [2]
Show answer
- (a) 1s at ABCD = 0101, 0111, 1101, 1111, 1001, 1011.Group B = 1, D = 1 (rows 01, 11; columns 01, 11) → B.DGroup A = 1, D = 1 (rows 11, 10; columns 01, 11) → A.DF = B.D + A.D
1 mark correct map/1s placed; 1 mark each group; 1 mark expression.
- (b) F = D.(A + B): A and B into an OR gate, its output and D into an AND gate.
1 mark factorised form; 1 mark circuit description.
Notation: ¬A means NOT A, A.B means A AND B, A + B means A OR B.Y = 1 for the minterms (ABCD) 0000, 0001, 0010, 0101, 1000, 1001, 1010, and Y = 0 otherwise.
- (a) Complete a Karnaugh map for Y (rows AB = 00, 01, 11, 10; columns CD = 00, 01, 11, 10). [2]
- (b) Write the simplest sum-of-products expression for Y. Describe the groups you have used. [4]
Show answer
- (a) AB \ CD | 00 01 11 1000 | 1 1 0 101 | 0 1 0 011 | 0 0 0 010 | 1 1 0 1
2 marks all correct; 1 mark one error.
- (b) Groups: four 1s at CD = 00, 01 in rows AB = 00 and 10 (wrap top/bottom) → ¬B.¬C; four corners → ¬B.¬D; pair AB = 00 and 01 at CD = 01 → ¬A.¬C.D.Y = ¬B.¬C + ¬B.¬D + ¬A.¬C.D
1 mark each correct group (wrap-round groups needed); 1 mark final expression with no redundant terms.
Notation: ¬A means NOT A, A.B means A AND B, A + B means A OR B.
- (a) Show, using Boolean algebra, that (A + B).(A + C) = A + B.C. State the laws you use. [4]
- (b) Explain why the simplified form is preferred when building the circuit. [1]
Show answer
- (a) (A + B).(A + C) = A.A + A.C + B.A + B.C (distributive law)= A + A.C + A.B + B.C (A.A = A, idempotent law)= A.(1 + C + B) + B.C (factorise)= A.1 + B.C = A + B.C (1 + X = 1; identity law)
1 mark expansion; 1 mark A.A = A; 1 mark factorise A; 1 mark reaching A + B.C.
- (b) It needs fewer gates (one AND and one OR instead of two OR and one AND), so the circuit is cheaper / faster / uses less power.
B1.
Notation: ¬A means NOT A, A.B means A AND B, A + B means A OR B.A fume extractor E in a university chemistry laboratory in Lahore is controlled by four inputs:G = 1 when gas is detectedT = 1 when the room temperature is highW = 1 when the windows are openM = 1 when the manual switch is onThe extractor runs (E = 1) if the manual switch is on, or gas is detected while the windows are closed, or gas is detected while the temperature is high.
- (a) Complete a Karnaugh map for E with rows GT = 00, 01, 11, 10 and columns WM = 00, 01, 11, 10. [3]
- (b) Write the simplified sum-of-products expression for E. Describe the groups used. [3]
Show answer
- (a) GT \ WM | 00 01 11 1000 | 0 1 1 001 | 0 1 1 011 | 1 1 1 110 | 1 1 1 0
The 1s are the minterms (GTWM) 0001, 0011, 0101, 0111, 1000, 1001, 1011, 1100, 1101, 1110, 1111. 3 marks all 16 cells; 2 marks one error; 1 mark two errors.
- (b) Groups: the eight 1s in columns WM = 01 and 11 → M; the four 1s in rows GT = 11 and 10 at WM = 00 and 01 → G.¬W; the four 1s in row GT = 11 → G.T.E = M + G.¬W + G.T
1 mark each term (groups as large as possible; overlapping allowed).
Notation: ¬A means NOT A, A.B means A AND B, A + B means A OR B.
- (a) Simplify X = ¬A.¬B.¬C + ¬A.¬B.C + ¬A.B.¬C + ¬A.B.C + A.B.¬C using Boolean algebra. Show each step. [4]
- (b) Confirm your answer by giving the groups you would loop on a 3-variable Karnaugh map. [2]
Show answer
- (a) = ¬A.¬B.(¬C + C) + ¬A.B.(¬C + C) + A.B.¬C= ¬A.¬B + ¬A.B + A.B.¬C= ¬A.(¬B + B) + A.B.¬C = ¬A + A.B.¬C= ¬A + B.¬C (using ¬A + A.Y = ¬A + Y)
1 mark first factorisation; 1 mark ¬A.¬B + ¬A.B; 1 mark ¬A; 1 mark final ¬A + B.¬C.
- (b) Group of four: the whole A = 0 row → ¬A. Pair: BC = 10 in both rows → B.¬C.
1 mark each group.
- (a) Complete the truth table for a half adder with inputs A and B, sum S and carry C. [2]
- (b) Name the logic gate that produces S and the gate that produces C. [2]
- (c) Explain why a half adder cannot be used on its own to add the second bit of two binary numbers. [1]
Show answer
- (a) A B | S C0 0 | 0 00 1 | 1 01 0 | 1 01 1 | 0 1
1 mark S column; 1 mark C column.
- (b) S: XOR gate. C: AND gate.
1 mark each.
- (c) It has no input for the carry from the previous (less significant) column, so a full adder (three inputs) is needed.
B1.
- (a) Complete the truth table for a full adder with inputs A, B and carry-in Cin, and outputs S and Cout. [4]
- (b) Describe how a full adder can be built from two half adders and one other gate. [2]
Show answer
- (a) A B Cin | S Cout0 0 0 | 0 00 0 1 | 1 00 1 0 | 1 00 1 1 | 0 11 0 0 | 1 01 0 1 | 0 11 1 0 | 0 11 1 1 | 1 1
2 marks S column (1 mark if one error); 2 marks Cout column (1 mark if one error).
- (b) The first half adder adds A and B; its sum and Cin go into the second half adder, whose sum output is S. The two carry outputs go into an OR gate, whose output is Cout.
1 mark arrangement of two half adders giving S; 1 mark carries ORed to give Cout.
An SR flip-flop is built from two cross-connected NOR gates. It has inputs S (set) and R (reset) and outputs Q and ¬Q (NOT Q).
- (a) Describe the effect on Q of each input combination: S = 1, R = 0; S = 0, R = 1; S = 0, R = 0; S = 1, R = 1. [4]
- (b) Q is initially 0. The inputs (S, R) are changed in this order: (1, 0), (0, 0), (0, 1), (0, 0), (1, 0). State the value of Q after each change. [2]
Show answer
- (a) S = 1, R = 0: Q is set to 1.S = 0, R = 1: Q is reset to 0.S = 0, R = 0: no change — Q keeps its previous value (the flip-flop stores the bit).S = 1, R = 1: invalid — both Q and ¬Q become 0, which is not allowed.
1 mark each.
- (b) 1, 1, 0, 0, 1
2 marks all five correct; 1 mark three or four correct.
- (a) Explain the role of flip-flops in a computer. [2]
- (b) State how many flip-flops are needed for a 64-bit register. [1]
- (c) Explain why a clock signal is used with flip-flops in a register. [2]
Show answer
- (a) Each flip-flop stores one bit (it is a bistable circuit that stays in a state until changed); groups of flip-flops form registers and static RAM (SRAM) / cache.
1 mark stores one bit / bistable; 1 mark used in registers / SRAM.
- (b) 64
B1 — one flip-flop per bit.
- (c) It synchronises the flip-flops so that all bits of the register change state at the same moment (on the clock pulse), preventing incorrect intermediate values being stored or read.
1 mark synchronise; 1 mark all bits change together / avoid errors.
- (a) Complete a table showing the effect on Q of a clock pulse for each combination of J and K. [4]
- (b) Q is initially 0. Six clock pulses arrive with (J, K) = (1, 0), (1, 1), (1, 1), (0, 0), (0, 1), (1, 1). State Q after each pulse. [2]
- (c) Give two advantages of a JK flip-flop over an SR flip-flop. [2]
Show answer
- (a) J K | Q after clock pulse0 0 | no change (Q)0 1 | 0 (reset)1 0 | 1 (set)1 1 | toggles (¬Q)
1 mark each row.
- (b) 1, 0, 1, 1, 0, 1
2 marks all six correct; 1 mark four or five correct.
- (c) No invalid state — J = K = 1 toggles the output instead; it is clocked/synchronised so outputs change only on a clock pulse, avoiding unpredictable changes.
1 mark each.
- (a) State how many full adders are needed for a 4-bit ripple-carry adder. [1]
- (b) The adder adds A = 1011 and B = 0110. Give the carry-out from each full adder, from the least significant bit to the most significant bit, and the final 4-bit sum and carry-out. [3]
- (c) Explain why a ripple-carry adder becomes slow for numbers with many bits. [2]
Show answer
- (a) 4 (or 3 full adders and one half adder for the least significant bit)
B1.
- (b) Carries (LSB → MSB): 0, 1, 1, 1Sum = 0001, final carry-out = 1
1 mark carries; 1 mark sum 0001; 1 mark final carry 1 (11 + 6 = 17 = 10001, which needs 5 bits).
- (c) Each full adder must wait for the carry from the previous stage before its outputs are correct, so the propagation delays add up — the delay grows in proportion to the number of bits.
1 mark waiting for carry; 1 mark delay accumulates with bit count.
- (a) Explain what is meant by a virtual machine. [2]
- (b) Give two benefits of using virtual machines. [2]
Show answer
- (a) Software that emulates a complete computer system (hardware), allowing a guest operating system and its programs to run as if on a separate physical computer, on top of a host system.
1 mark software emulation of hardware/computer; 1 mark guest OS runs on host.
- (b) Any two: several operating systems can run on one physical machine; software for one platform can run on another; a crash or malware in a VM does not affect the host / other VMs; easy to back up, copy or restore (snapshots); saves hardware costs.
1 mark each.
A developer in Lahore is writing a desktop application that must work on three different operating systems.
- (a) Explain why the developer uses virtual machines to test the app on different operating systems. [3]
- (b) State one limitation of testing in a virtual machine. [1]
Show answer
- (a) 1 mark each, max 3:• several operating systems can be tested on one computer, so no need to buy many machines• a VM can be reset to a clean snapshot before each test• if the app crashes the OS, only the VM is affected, not the host• it is quick to create VMs for different OS versions
- (b) e.g. performance is lower than on real hardware, so speed tests are unreliable / some hardware features (e.g. GPU, sensors) may not be available.
B1.
A shipping company in Karachi still uses a cargo-tracking program that runs only on an old operating system. It has bought new servers and wants to run the old program in virtual machines.
- (a) Explain three benefits to the company of running the old system in virtual machines on its new servers. [3]
- (b) Explain two limitations of this approach. [2]
Show answer
- (a) 1 mark each, max 3:• the old software can keep running even though it is not compatible with the new hardware / OS• several old and new systems can share one powerful server, saving hardware and energy costs• the old system is isolated, so if it crashes or is infected it does not affect other systems• snapshots allow the VM to be backed up and restored quickly / moved to another server
- (b) 1 mark each: the VM runs more slowly than on real hardware because instructions are translated / the hypervisor adds overhead; the VM may not emulate some hardware (e.g. special devices) correctly; extra memory and processing is needed; licences still needed for each guest OS.
- (a) Explain how the use of a virtual machine allows the same Java program to run on Windows, Linux and Android devices. [3]
- (b) State one drawback of running programs in a process virtual machine such as the JVM. [1]
Show answer
- (a) 1 mark each:• the source code is compiled into intermediate code (bytecode), not machine code for one processor• each platform has its own Java Virtual Machine (JVM)• the JVM interprets / just-in-time compiles the bytecode into machine code for that platform, so the same bytecode runs anywhere a JVM exists
- (b) Slower execution than native machine code / needs the JVM installed / uses extra memory.
B1.
A computer science department in Islamabad runs a Linux guest operating system inside a virtual machine on Windows host computers.
- (a) Describe the roles of the host operating system, the hypervisor (virtual machine software) and the guest operating system in this set-up. [3]
- (b) Explain how an instruction from an application in the guest OS to write to disk is carried out. [2]
- (c) Explain why software tested in a virtual machine may still behave differently on real hardware. [1]
Show answer
- (a) Host OS: runs directly on the physical hardware and controls the real resources.Hypervisor: creates and manages the VMs, allocating memory, processor time and storage to each, and translates / passes the guest's requests to the host.Guest OS: runs inside the VM, believes it controls its own hardware, and runs the user's applications.
1 mark each.
- (b) The guest OS issues the request to its virtual disk; the hypervisor intercepts it and translates it into a request to the host OS / real hardware, which writes the data to a file representing the virtual disk.
1 mark intercepted by hypervisor; 1 mark translated and carried out by host / real hardware.
- (c) The VM emulates hardware, so timing / performance and some devices differ from the real machine.
B1.
- (a) Describe each of these computer architectures: SISD, SIMD, MISD, MIMD. [4]
Show answer
- (a) SISD: single instruction, single data — one processor carries out one instruction on one data item at a time.SIMD: single instruction, multiple data — several processors carry out the same instruction on different data items at the same time.MISD: multiple instruction, single data — several processors carry out different instructions on the same data.MIMD: multiple instruction, multiple data — several processors each carry out different instructions on different data (e.g. multicore computers).
1 mark each.
- (a) Identify the most suitable architecture for each task and justify your choice.(i) Increasing the brightness of every pixel in a large photograph.(ii) A multicore laptop running a browser, a music player and a word processor at the same time. [4]
- (b) Explain what is meant by a massively parallel computer. [2]
Show answer
- (a) (i) SIMD — the same instruction (add a brightness value) is applied to many pixels (data items) at once.(ii) MIMD — each core runs different instructions (different programs) on different data.
1 mark each architecture; 1 mark each justification.
- (b) A computer with a very large number of processors (hundreds/thousands or more) that work simultaneously on parts of one problem, linked by a network / interconnect so they can communicate.
1 mark very many processors; 1 mark working together on one task / communicating.
The national meteorological department in Pakistan uses a massively parallel computer to produce monsoon forecasts.
- (a) Describe the characteristics of a massively parallel computer system that make it suitable for weather forecasting. [3]
- (b) Explain why the software must be specially written for this computer. [2]
- (c) Explain why some problems do not run much faster on a massively parallel computer. [1]
Show answer
- (a) 1 mark each, max 3:• thousands of processors work simultaneously• the forecast area can be split into many grid cells, each handled by a different processor• processors are linked by a high-speed network to exchange results for neighbouring cells• each processor has its own memory, so huge amounts of data can be processed at once
- (b) The program must be split into tasks that can run at the same time (parallel algorithms), and must coordinate / synchronise the processors and the data they share.
1 mark split into parallel tasks; 1 mark coordination / communication.
- (c) If each step depends on the result of the previous step, the work cannot be divided, so most processors would be idle / communication overheads outweigh gains.
B1.
- (a) Describe four differences between RISC and CISC processors. [4]
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- (a) 1 mark each, max 4:• RISC has fewer, simpler instructions; CISC has many complex instructions• RISC instructions are mostly executed in one clock cycle; CISC instructions take several cycles• RISC instructions have a fixed length; CISC instructions vary in length• RISC has fewer addressing modes; CISC has many• RISC uses many general-purpose registers; CISC has fewer• RISC is hard-wired control; CISC often uses microprogrammed control• RISC is easier to pipeline• RISC programs need more instructions / more RAM; CISC programs are shorter (more work for the compiler with RISC)
Each difference must compare both.
A processor uses a 5-stage pipeline: instruction fetch (IF), instruction decode (ID), operand fetch (OF), instruction execute (IE) and write back (WB). Each stage takes one clock cycle. Assume there are no branches or interrupts.
- (a) Calculate how many clock cycles are needed to complete 8 instructions with pipelining, and how many without pipelining. Show your working. [3]
- (b) State which instruction is in each stage during clock cycle 4. [2]
- (c) Explain why RISC processors are well suited to pipelining. [2]
Show answer
- (a) With pipelining: 12 cycles. Without pipelining: 40 cycles.
M1 first instruction takes 5 cycles, then one more instruction completes every cycle: 5 + (8 − 1) = 12A1 12B1 without pipelining 8 × 5 = 40
- (b) Instruction 1 in IE (execute), instruction 2 in OF (operand fetch), instruction 3 in ID (decode), instruction 4 in IF (fetch); the WB stage is empty.
2 marks all correct; 1 mark two or three correct.
- (c) RISC instructions are of fixed length and most take one clock cycle, so each stage takes the same time and the stages stay in step / the pipeline flows smoothly.
1 mark fixed length / one cycle; 1 mark stages balanced.
A RISC processor uses a 5-stage pipeline.
- (a) Explain the problem caused when an interrupt occurs in a pipelined processor, and describe one way it can be handled. [3]
- (b) Explain how a conditional branch (jump) instruction reduces the performance of the pipeline. [2]
- (c) State one technique used to reduce this loss. [1]
Show answer
- (a) Problem: several instructions are partly processed in different stages when the interrupt arrives, so the processor state cannot be saved simply by storing one program counter value.Handling (any one, 2 marks): the instructions in the early stages are flushed/erased, the instruction(s) already in the execute stage are completed, and the address of the next instruction to restart is saved before the interrupt service routine runs; OR each stage has its own program-counter register so the contents of the pipeline can be saved and restored after the interrupt.
1 mark problem; 2 marks a described method.
- (b) The next instructions are fetched in sequence before the branch is executed; if the branch is taken, these instructions are wrong and must be discarded (pipeline flushed), so cycles are wasted until the pipeline refills.
1 mark wrong instructions already fetched; 1 mark flush / wasted cycles.
- (c) Branch prediction / speculative execution / delayed branch (filling the slot after a branch with a useful instruction).
B1.
